1. Field of the Invention
The present invention relates to a multilayer system including a multilayer switch which allows simultaneous processing of commands from a plurality of masters and a clock control method in the multilayer system.
2. Description of Related Art
Recent mobile phones have become multifunctional, having not only telephone functions but also internet connection functions, camera functions and so on. Further, in order to realize downsizing, weight saving, and reduction in power consumption, System on Chip (SoC) technology which incorporates multiple functions on one chip has been developed.
Such mobile phones require high speed, simultaneous processing. Thus, a multilayer switch which allows simultaneous access to a plurality of slaves has been proposed.
Use of the multilayer switch permits to carry out a process of writing image data from a camera into a given memory region and a process of reading the image data stored in the memory and displaying it on a screen at the same time.
FIG. 5 shows a configuration example of a system including a multilayer switch. A plurality of master modules (hereinafter simply as “masters”) 11 and slave modules (“slaves”) 13 are connected to a multilayer switch module (“multilayer switch”) 12. The multilayer switch 12 includes a switch master portion 120 connected to each master 11 and a switch slave portion 121 connected to each slave 13.
A clock generator 14 constantly supplies clock signals to the masters 11, the multilayer switch 12, and the slaves 13.
FIG. 6 shows a layout example of circuits on one chip. For example, an M0 which is the master 11 such as a CPU is placed at a corner. Other modules such as SWM0, SWS0, S0, and S1 are arranged on the chip in a dispersed manner. A clock signal is constantly supplied to each module from the clock generator 14.
Each module receives a clock signal and operates, thereby consuming power. A drive buffer 15 is placed in a line between each module and the clock generator 14 in order to prevent deterioration of a signal waveform or control timing. If a line length from each module to the clock generator 14 is long, many drive buffers 15 are placed as shown in FIG. 6. The drive buffer 15 also consumes power due to a through current when the output of a transistor changes from high to low or from low to high.
Japanese Unexamined Patent Application Publication No. 2003-141061 discloses a technique that supplies power to only some of a plurality of buses in a normal bus configuration. However, these buses do not have a multilayer switch function that allows simultaneous processing of commands from a plurality of masters.
As described above, the present invention has recognized that a conventional multilayer system requires a large amount of power since it supplies clock signals to all of the masters, slaves, and multilayer switch.